Control of a DC matrix converter

ABSTRACT

A DC matrix converter having six forward current conducting power switches and six reverse current conducting power switches has the on time duration of each power switch within a pulse width modulation period controlled by relationships between d and q components of a modulation index determined by the ratio of a voltage command to the instantaneous voltage of the AC mains expressed in stationary dq coordinates, the selection of which is made based on inequalities between the DC main voltage components expressed in stationary dq coordinates. Switch selection is also performed in response in relationships of the AC main voltage components expressed in stationary dq coordinates. Zero vectors are selected to minimize the common mode voltage.

TECHNICAL FIELD

This invention relates to controlling a direct, AC to DC matrixconverter to supply controlled DC voltage to a load utilizing preciselycontrolled, pulse width modulation.

BACKGROUND ART

In commonly owned, copending U.S. patent application Ser. No. 09/310,600filed contemporaneously herewith, a direct, 3-phase AC to DC matrixconverter employs switches which are controlled in sequence to directlysynthesize a desired average DC voltage waveform at the input terminalsof the DC motor, while simultaneously distributing the DC output currentamong the AC input lines as a sinusoidal waveform in phase with the ACvoltage. The difference between the direct DC matrix converter of saidcopending application and prior DC-PWM converters is that the priorconverters create a DC power of a fixed voltage, much the same as abattery, and then utilized some portion of the voltage, as needed,synthesizing a correct DC voltage, on average, by means of pulse widthmodulation, whereas in said application, the desired voltage at thedesired current is synthesized by pulse width modulation directly fromthe AC mains, while retaining the sinusoidal balance and unity powerfactor of the AC input currents.

In the system of said application, each switch is turned on and off ineach modulation period. As is known, the switching losses in powerswitches occur only during transition between the non-conducting andconducting states; therefore, reducing the number of commutations willsignificantly reduce power losses in the switches.

DISCLOSURE OF INVENTION

Objects of the invention include providing pulse width modulationsynthesis of DC voltage directly from three-phase AC mains with minimalcommutation losses, with a minimum of calculations (processor steps),with modulation frequencies as high as 10 KHz or more to provide minimalripple in the DC voltage and current, with minimal distortion and aunity power factor at the AC mains.

This invention is predicated on my discovery that all switches in a DCmatrix converter can be turned on and remain on for two out of threeportions of the same or adjacent pulse width modulation periods, whenoperated in a proper sequence, including two voltage producing portionsand one non-voltage producing portion of each pulse width modulationperiod.

According to this invention, the switch-on time of DC matrix powerswitches is determined by the ratio of an instantaneous voltage commandsignal, V*, (indicative of the voltage to be provided by said DC matrixconverter) to the instantaneous magnitude, V, of the three-phase ACmains in stationary dq coordinates, along with the phase relationshipbetween the present instantaneous phase of said AC mains voltage instationary dq coordinates and the leading and lagging boundaries of sixphase sectors that span a cycle of said AC mains.

According to the invention further, the phase relationship are expressedin terms of dq quantities, using trigonometric angle-sum relationshipsand identified by inequalities existing between the voltages of the ACmains expressed in orthogonal dq coordinates and zero.

In still further accord with the invention, the pairs of switches to beused in each portion of a pulse width modulation period are selected byrelationships between the components of the AC mains voltage inorthogonal DQ coordinates. The invention may be implemented in DC matrixconverters which supply unilateral current, bilateral current, and withor without regeneration.

Other objects, features and advantages of the present invention willbecome more apparent in the light of the following detailed descriptionof exemplary embodiments thereof, as illustrated in the accompanyingdrawing.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram of an elevator system employing a DCmatrix converter controlled in accordance with the present invention.

FIG. 2 is a schematic diagram of a common emitter, DC matrix converterwhich may be controlled in accordance with the present invention.

FIG. 3 is a plot of AC mains voltage including designations of currentvectors related to the present invention.

FIG. 4 is a space-vector diagram illustrating principles of the presentinvention.

FIGS. 5 and 6 are diagrams illustrating various parameters of theinvention in various sectors of a cycle.

FIG. 7 is a space-vector diagram illustrating inequalities used tocontrol a DC matrix in accordance with the present invention.

FIG. 8 is a simplified logic flow diagram of an exemplary routine fordetermining switch-on durations in accordance with the invention.

FIGS. 9-12 are diagrams illustrating sectors of a cycle in which variousswitches may be operated.

FIG. 13 is a logic flow diagram of a non-zero vector switch selectionroutine (simplified exemplary).

FIG. 14 is a space-vector diagram illustrating inequalities used toselect zero vectors.

FIG. 15 is a simplified, logic flow diagram of an exemplary zero vectorswitch selection routine.

FIGS. 16a-c are a series of waveforms on a common phase base,illustrating principles of the invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Referring to FIG. 1, a DC matrix converter 18 provides current to a DCmotor 19, which in this embodiment is shown mechanically connected to asheave 20 which is connected by roping 21 to an elevator car 22 and acounterbalance 23. The DC matrix converter 18 selectively connectsvarious pairs of the three-phase AC mains a, b, c directly to the outputterminals of the converter j, k. The voltage can be positive at terminalj and negative at terminal k, and conventional positive current flowingfrom terminal j to terminal k, such as, for instance, when the elevatoris being driven upwardly with a heavy load, or terminal k can bepositive, terminal j negative and conventional positive current flowingfrom k to j, such as, for instance, when the elevator is being drivendownwardly with a light load; this is called “motoring”. Whenever theelevator is traveling upwardly with a light load, downwardly with aheavy load, or is decelerating, the sheave 20 will actually drive themotor 19 so that the motor 19 acts as a generator. In such a case, thepositive current flow through the motor 19 will be of opposite polarityfrom the polarity of voltage at the terminals j, k; this is called“regeneration”. The DC matrix converter 18 will connect the switchesappropriately in dependence upon magnitude and direction of a speedcommand provided to the DC matrix converter controller of FIG. 1, andwhether the motor 19 is operating in a motoring mode or in aregeneration mode.

In the example herein, the commands which will ultimately cause the DCmatrix converter to drive the motor 19 in a desired fashion are providedby a conventional elevator motion controller (not shown) which providesa speed command on a line 30 to a summer 31 which subtracts the actualspeed on the line 32 provided by a conventional position and speedconversion circuit 33 in response to a signal on a line 34 from asuitable, conventional encoder (not shown) which is coupled to thesheave 20 (or the motor 19, as the case may be). A position output ofthe circuit 33 on a line 37 is fed back to the motion controller so asto determine the continuity of commands necessary to cause the elevatorto move in the desired fashion, all as is well known in the art andforms no part of the present invention. The output of the summer 31 isprovided on a signal line 40 to a conventional speed error proportionaland integral gain circuit 41, the output of which on a line 42 comprisesa current command, I*, which is fed to a summer 43. The summer 43subtracts the actual motor current on a line 44, derived from aconventional current sensor 45 to provide a current error signal on aline 46. The current error signal is processed with conventionalproportional and integral gain in a circuit 51, the output of which on aline 52 comprises a voltage command, V*.

In accordance with the invention, the ratio of the magnitude of thevoltage command to the magnitude of the input AC mains voltage vector,in stationary dq coordinates, determines a modulation index, m*, whichis used to determine the duration of switch-on time during pulse widthmodulation of the voltage on the AC input mains in order to achieve thedesired DC voltage for application to the load, such as the motor 19.

The voltage on the AC mains a, b, c is fed to a conventional stationarythree-phase to stationary dq coordinate conversion circuit 56 to provideoutputs Vd, Vq which define the three-phase input voltages of the ACmains in orthogonal coordinates, as is known. The magnitude of the ACmains, V, on a line 57, is simply the square root of the sum of thesquares of Vd, Vq, performed in a conventional unit 58. The orthogonalmagnitudes Vd, Vq are also fed to a conventional phase locked loop 63,the output of which on lines 65 and 66 are signals indicative of sine Θand cosine Θ, respectively. These are applied to a circuit 68 whichconverts the modulation index m* in synchronous dq coordinates todesired modulation index components mq, md in stationary dq coordinates.The mq and md signals on lines 71, 72 are fed to a duration andselection function 73 which determines the duration for which a selectedpair or set of switches should be turned on, and selects which pair orset of switches are to be on, at any given moment, to perform thenecessary pulse width modulation in order to synthesize the desired DCvoltage at the output terminals, j, k, of the DC matrix converter 18.The functions 73 are described more fully hereinafter. Signalsindicative of the duration of switch on times, and the selected pair ofswitches to be turned on, are provided over a trunk of lines 77 totiming circuits 78 which actually count pulses in real time so as toimplement the desired durations by providing switch on gating circuitsover a trunk of 12 lines 79 to the DC matrix converter 18. The timingcircuits turn the switches on and off according to conventionalcommutation methods, so that each of the output terminals is alwaysconnected to an AC main, with no open circuit gaps, to satisfy the knowncontinuity of current constraint. One commutation example is set forthin Holmes and Lipo, “Implementation of a Controlled Rectifier UsingAC—AC Matrix Converter Theory”, IEEE Trans, Power Elec., January, 1992.

Although not shown in FIG. 1, the DC matrix converter of the inventionrequires line-to-line capacitance across the AC input to support switchcommutation described hereinafter. These may be included along within-line inductors within an input filter 82. Similarly, the DC matrixconverter preferably has an output filter 83 with series inductance andshunt capacitance, both filters being shown in the aforementionedapplication.

One embodiment of a DC matrix converter 18 is illustrated in FIG. 2. Foreach phase of the AC mains, a, b, c there are two power transistorswitches at the top of FIG. 2 and two switches at the bottom of FIG. 2.One switch at the top of FIG. 2, at+, bt+, ct+ will conduct current fromthe corresponding one of the AC mains through the terminal j to themotor 19 while one of the corresponding bottom switches ab+, bb+ cb+will conduct current from the motor 19, through the terminal k to thecorresponding one of the AC mains. For purposes of illustration herein,flow of current from the terminal j, downwardly through the motor 19 tothe terminal k is deemed to be positive current flow. For negativecurrent flow, one of the negative bottom switches ab−, bb−, cb− willconduct current from the corresponding one of the AC mains, through theterminal k, through the motor 19, to the terminal j, and one of the topnegative switches at−, bt−, ct− will conduct current from the terminal jto a corresponding one of the AC mains.

The general nature of operation of the DC matrix converter isillustrated in FIG. 3. Therein, the sinusoidal voltage of the AC mainsVa, Vb, Vc is plotted against time. Also plotted in FIG. 3 are aplurality of different current vectors i1, i2 . . . i6 which can resultfrom various combinations of conducting power transistor switches at+,bt+ . . . cb− in FIG. 2. These appear as vertical arrows extending froma negative voltage to a positive voltage. Associated with each verticalarrow is a horizontal arrow bearing the same designation in parenthesis,which indicates the portion of each cycle within which the correspondingcurrent vector may be switched (about fifty-five times per cycle in theexample hereinafter) to produce positive voltage at the output terminals(Vj>Vk) whenever the input command is positive (m*>0). In each instance,the top portion of the arrow is designated as current flowing through aswitch designated a, b or c, the designation At indicating that eitherthe transistor at+ or the transistor at− will be conducting at thatparticular time, depending upon whether current flow is to be positiveor negative, as described hereinbefore. Similarly, the designation Cbfor the current vector i1 indicates that one of the transistors cb+,cb−, will be conducting in dependence upon whether the current flow isto be positive or negative, respectively. Thus, for the current vectori1 (whether it be positive or negative, as described hereinafter) isachieved by connecting phase c of the AC mains and phase a of the ACmains to the terminals k and j of the matrix, respectively. The currentvector i1 can exist in time from the point where Vc=0 to the point whereVa=0.

The commanded modulation index, m* for the DC matrix converter istransformed to the stationary reference frame, in dq coordinates, asfollows:

md=m* sin Θ

mq=m* cos Θ0<Θ<2π

where Θ=0 corresponds to the q-axis of the AC mains voltage in thesynchronous reference frame (63-68, FIG. 1).

The currents i1-i6 are the only possibilities that produce non-zerovoltage at the output terminals (Vj not equal to Vk), which can beachieved by selective operation of two of the switches in FIG. 2 at onetime. For instance, if switch at+ is operated simultaneously with switchbb+ in FIG. 2, this will result in current i6 as illustrated in FIG. 3.If at+ is operated simultaneously with cb+, this will result in currenti1 of FIG. 3. If at+ is operated simultaneously with ab+, this shortcircuits the terminals j, k with no differential voltage produced at theoutput terminals (Vj=Vk), with current circulating through the at+ andab+ switches, which is defined herein as a zero vector. The synthesis ofthe DC voltage is accomplished by pulse width modulation at a frequencywhich is very high with respect to the frequency of the AC mains, suchas 10 KHz, resulting in a short modulation period, such as 100 μs.Within each 100 μs modulation period, a first pair of switches (such asAt, Bb) will be conducting for some fraction of the modulation period(defined as “duty ratio” and as “duration”), a second pair of switches(such as At, Cb) will be conducting for some portion of that modulationperiod, and a zero vector formed by a set of switches related to thesame phase, such as Bt, Bb will be conducting for the remaining fractionof time to provide a zero vector, as described hereinafter.

Referring to FIG. 4, a space vector diagram, illustrating themethodology for controlling the DC matrix converter, includes each ofthe current vectors i1-i6 which result from turning on a selected pairof switches, as described hereinbefore. The current vectors i1-i6 areboundaries separating six phase sectors, s=0, . . . s=5. Each boundaryis a lagging boundary for one phase sector and a leading boundary forthe next following phase sector. In FIG. 4, a particular torque currentreference, i*, for a case when positive output voltage is to be produced(m*>0), is illustrated within a modulation period which exists at apoint in time when i6 may be utilized and when i1 may be utilized. Thisis defined as phase sector zero (s=0). The resulting modulation index m*and related quantities md, mq are also shown. For the modulation perioddepicted in FIG. 4, a leading current vector (or boundary) defined as Iαis the current vector i6, and a lagging current vector (or boundary)defined as Iβ is the current vector i1. The duty ratios, or durations oftime, dα, dβ, that pairs of switches are turned on, for correspondingcurrent vectors Iα, Iβ, in order to approximate the reference vector,i*, is proportional to the sine of the angle between the referencevector and the corresponding leading and lagging current vectors Iα, Iβ.The duty ratios to be used in each sector are given by

dα=m* sin (π/3−φ) dβ=m* sin (φ) 0<φ<π/3

d0=1−dα−β.

where φ=0 and φ=π/3 correspond to the angular location of the α-vectorand β-vector, respectively.

In further accord with the invention, to determine the switch times, theabove modulation functions are expressed in terms of dq quantities byusing trigonometric angle-sum relations in each sector as follows. Usingthe above equations and the fact that φ=π/6+Θ−sπ/3, where s is thesector in FIG. 4, for 0<s<5, one can express $\begin{matrix}{{d\quad \alpha} = \quad {m^{*}\sin \left\{ {{{\pi/3} - \left( {{\pi/6} + \theta - {s\quad {\pi/3}}} \right\}} = {m^{*}{\sin\left( {{\pi/6} + {s\quad {\pi/3}} - \theta} \right\}}}} \right.}} \\{= \quad {{m^{*}{\sin\left\lbrack {{\pi/6} + {s\quad {\pi/3}}} \right)}\cos \quad \theta} - {m^{*}{\cos \left( {{\pi 6} + {s\quad {\pi/3}}} \right)}\sin \quad \theta}}} \\{= \quad {{{\sin \left( {{\pi/6} + {s\quad {\pi/3}}} \right)}{mq}} - {{\cos \left( {{\pi/6} + {s\quad {\pi/3}}} \right)}{md}}}}\end{matrix}$ and $\begin{matrix}{{d\quad \beta} = \quad {{m^{*}\sin \left\{ {{\pi/6} + \theta - {s\quad {\pi/3}}} \right\}} = {m^{*}{\sin \left( {{\pi/6} - {s\quad {\pi/3}} + \theta} \right)}}}} \\{= \quad {{m^{*}{\sin\left\lbrack {{\pi/6} + {s\quad {\pi/3}}} \right)}\cos \quad \theta} + {m^{*}{\cos \left( {{\pi 6} + {s\quad {\pi/3}}} \right)}\sin \quad \theta}}} \\{= \quad {{{\sin \left( {{\pi/6} - {s\quad {\pi/3}}} \right)}{mq}} + {{\cos \left( {{\pi/6} - {s\quad {\pi/3}}} \right)}{md}}}}\end{matrix}$

For reference, the values of the sine and cosine coefficients in theabove equations are given in the following table, for each sector s=0through s=5.

sin(π/6 + −cos (π/6 + sin(π/6 − −cos(π/6 − s s π/3) s π/3) s π/3) s π/3)0  ½ −3/2  ½  3/2 1  1 0 −½  3/2 2  ½  3/2 −1 0 3 −½  3/2 −½ −3/2 4 −1 0 ½ −3/2 5 −½ −3/2  1 0

If the following quantities are defined:${m1} = {{\frac{\sqrt{3}}{2}{md}} - {\frac{1}{2}{mq}}}$${m2} = {{\frac{\sqrt{3}}{2}{md}} + {\frac{1}{2}{mq}}}$

then the modulation functions (α and β duty ratios) are determined ineach sector by the quantities given in the following table:

s dα dβ 0 −m1  m2 1  mq  m1 2  m2 −mq 3  m1 −m2 4 −mq −m1 5 −m2  mq

This is illustrated in the space-vector diagrams of FIGS. 5 and 6. Thus,the duty cycles for both vectors dα and dβ are determined solely by thequantities mq, m1 and m2, which can be easily calculated on a digitalsignal processor using the foregoing equations as shown in steps 101-104in FIG. 8.

During a modulation period which is at the beginning of a sector, theswitching time for the α vector will be significant, and the switchingtime for the β vector will be slight. Midway through the sector, theswitching time for the α vector will be equal to the switching time ofthe β vector. Near the end of a sector, the on-time for the β vectorwill be significant and the on-time for the α vector will be slight. Inthe remainder of each modulation period, d0=1−dα−dβ (the duration forthe zero vector), a pair of switches related to the same AC main, suchas Bt, Bb, will be turned on so as to provide a zero vector, therebyadjusting the magnitude of the output voltage while utilizing a minimumnumber of switch commutations. The times when the various top switcheswill be turned on so as to conduct an α vector are shown in FIG. 9, andthe times to conduct a β vector are shown in FIG. 10. The times thevarious bottom switches are turned on so as to conduct an α vector areshown in FIG. 11, and the times when they are turned on so as to conducta β vector are shown in FIG. 12. When to apply each quantity (mq, m1,m2) necessitates a determination of the sector in which the AC mainsinput voltage vector lies, which is accomplished with inequalitytesting, and testing whether m* is positive or negative. Theinequalities that define the sector boundaries for m*>0 are shown inFIG. 7. Therein, Vd and Vq refer to the input AC mains voltage instationary coordinates (56, FIG. 1). For negative commands (m*<0) thecurrent vector I* is shifted by π radians from that shown in FIG. 4. Thefollowing table shows the quantities to use in selecting the top andbottom α and β switches.

m* > 0 m* < 0 Top Vd′ = Vd Vd′ = −Vd Switches Vq′ = Vq Vq′ = −Vq BottomVd′ = −Vd Vd′ = Vd Switches Vq′ = −Vq Vq′ = Vq

Therefore, test 107 and steps 108-111 define Vd′ and Vq′ appropriatelyfor the sign of m* before the inequalities are tested. From FIG. 6,|dβ|=m2 in sectors 0 and 3, which are defined by the followinginequality:$\left\lbrack {{Vd} > {{{- {Vq}}/\sqrt{3}}\bigcap{Vd}} < {{Vq}/\sqrt{3}}} \right\rbrack\bigcup{\left\lbrack {{Vd} < {{{- {Vq}}/\sqrt{3}}\bigcap{Vd}} > {{Vq}/\sqrt{3}}} \right\rbrack \left\lbrack {{{Vd}} < {{Vq}/\sqrt{3}}} \right\rbrack}\bigcup\left\lbrack {{{Vd}} < {{- {Vq}}/\sqrt{3}}} \right\rbrack$${{{Vd}\sqrt{3}}} < {{Vq}}$

This is easily tested for on a digital signal processor as shown in test115 of FIG. 8. Similarly, |dβ|=m1 in sectors 1 and 4, which are definedby the following inequality:$\left\lbrack {{{V\lbrack d\rbrack}q} < {0\bigcap{Vd}} < {{Vq}/\left. \sqrt{}3 \right.}} \right\rbrack\bigcup{\left\lbrack {{Vq} > {0\bigcap{Vd}} > {{Vq}/\left. \sqrt{}3 \right.}} \right\rbrack \left\lbrack {{VdVq} > {{Vq}^{2}/\left. \sqrt{}3 \right.}} \right\rbrack}\bigcup\left\lbrack {{VdVq} > {{Vq}^{2}/\left. \sqrt{}3 \right.}} \right\rbrack$${{VdVq}\left. \sqrt{}3 \right.} > {Vq}^{2}$

This is determined in test 116 of FIG. 8.

The remaining sectors, 2 and 5, in which |dβ|=mq, are determined throughthe process of elimination (tests 115 and 116 negative, FIG. 8). Thesign of dβ is determined by testing the sign of Vq in tests 117-119 ofFIG. 8; i.e., dβ=−dβ if Vq<0, as shown in steps 120-122 117-119, FIG. 8.

The duty ratio din dα is easily obtained by noting in FIG. 5 that dα isshifted 2π/3 radians relative to dβ, in FIG. 6. Hence, the determinationof dα is identical to the assignments above by using the followingsubstitution when testing the above equalities:${Vd}^{''} = {{{- \frac{1}{2}}{Vd}^{\prime}} - {\frac{\sqrt{3}}{2}{Vq}^{\prime}}}$${Vq}^{''} = {{{- \frac{1}{2}}{{Vq}^{\prime}\lbrack - \rbrack}} \pm {\frac{\sqrt{3}}{2}{Vd}^{\prime}}}$

This is achieved by steps 123 and 124 (FIG. 8) which make thesubstitution, and steps and tests 125 which repeat steps and tests115-122, etc.

Once the on-times are determined for the α and β vectors, it isnecessary to determine which switches are to be turned-on to produce thevectors according to FIG. 4. This is a two-step process: a determinationof switches for the non-zero vectors, followed by switch assignments forthe zero vector.

The phases (i.e., switches) to which the above duty ratios or durationsapply are determined by the region in which the voltage vector lies. Forexample, the switch assignments for the top power switches in the DCmatrix converter for the α vector and β vector are shown in FIGS. 9 and10. If the vector lies in one of the sectors denoted Bt, then the switchassignment is made to Bt. Referring to FIG. 10, for switch Bt, thesectors s=1 or s=2 can be jointly identified by testing the followinginequality (test 130, FIG. 13):$\left\lbrack {{Vd}^{\prime} > {{- {Vq}^{\prime}}/\sqrt{3}}} \right\rbrack\bigcap\left\lbrack {{Vd}^{\prime} > {{Vq}^{\prime}/\sqrt{3}}} \right\rbrack$${{Vd}^{\prime}\sqrt{3}} > {{Vq}^{\prime}}$

The remaining assignments of top switches for the β-vector aredetermined, after eliminating sectors 1 and 2, by testing the sign of Vqas shown in FIG. 7; if Vq′>0 (test 131 affirmative), the sector is 0 or5 and the top β switch is At; if Vq<0 (test 131 negative), the sector is3 or 4, and the top β switch is Ct.

The top switch assignments for the α-vector are easily obtained bynoting in FIG. 9 the phase shift of π/3 radians relative to the topswitch assignment for the β-vector in FIG. 10. Hence, the determinationof the top switch for the α-vector is identical to the assignments aboveif the following substitutions are first made (steps 135, 136, FIG. 13):

Vd′ Vd″=½Vd′−3Vq′/2

Vq′ Vq″=− ½Vq′+3Vd′/2

These assignments are shown in tests and steps 138 of FIG. 13.

Determination of bottom switch assignments for the α-vector and β-vectoris identical to the above except for a phase shift of π radians betweenthe assignments for the two groups. Hence, the determination isidentical to the above when using the following substitutions (steps140, 141, FIG. 13):

Vd″=−Vd″

Vq″=−Vq″

These selections are made in steps and tests 143 of FIG. 13.

As described hereinbefore, a zero vector, i0, is defined as the shortcircuiting of the output terminals j, k by a set of like-phase switches,At, Ab; Bt, Bb; Ct, Cb. The selection of which set of switches to use inrepresenting the zero vector affects the common-mode output voltage. Theapplication of each vector, i1-i6, results in each of the outputterminals, j, k, to be connected to one of the AC main voltages Va, Vb,or Vc. The differential voltage applied across the load, VD, is thedifference in the output phase voltages, Vj−Vk, while the common-modevoltage referenced to the system neutral, VCM, is the sum of the twooutput line voltages divided by the number of output phases, (Vj+Vk)/2.The resulting differential and common-mode voltages produced by eachvector is given in the following tables:

Vector i1 i2 i3 i4 i5 i6 i0 i0 i0 Switches At, Cb Bt, Cb Bt, Ab Ct, AbCt, Bb At, Bb At, Bb Bt, Bb Ct, Cb Vj VC VC VA VA VB VB VA VB VC Vk VAVB VB VC VC VA VA VB VC VD VAC VBC VBA VCA VCB VAB 0 0 0 VCM VA + VCVB + VC VB + VA VC + VA VC + VB VA + VB VA VB VC

Since the line voltages Va, Vb, and Vc are sinusoidal, the peakcommon-mode voltage attained by the non-zero vectors, i1 through i6,over an AC cycle is easily calculated as

VCM(peak)=½⅔VLL, 0<ωt≦2π

where VLL is the rms line-to-line voltage and wt is the AC phase anglein radians. In contrast, the peak common-mode voltage attained by thezero vectors during the same period is

VCM(peak)=⅔VLL, 0<ωt≦2π

As a consequence, an indiscriminant use of the zero vectors results in apeak common-mode voltage which is twice that for the non-zero vectors.

The zero vectors can, however, be chosen in such a way as to reduce thepeak common-mode voltage. For example, if the use of the zero vector(At, Ab) is restricted to the periods$\frac{\pi}{3} \leq {\omega \quad t} \leq {\frac{2\pi}{3}\quad {and}\quad \frac{4\pi}{3}} \leq {\omega \quad t} \leq \frac{5\pi}{3}$

where ωt=0 corresponds to the peak of the line voltage Va, the maximumcommon mode voltage is given by:${{{VCM}({peak})} = {\sqrt{\frac{2}{3}}{VLL}\quad {\cos \left( \frac{\pi}{3} \right)}}},{\frac{\pi}{3} < {\omega \quad t} \leq {\frac{2\pi}{3}\quad {or}\quad \frac{4\pi}{3}} < {\omega \quad t} \leq \frac{5\pi}{3}}$

which equals${{{VCM}({peak})} = {\frac{1}{2}\sqrt{\frac{2}{3}}{VLL}}}\quad,{\frac{\pi}{3} < {\omega \quad t} \leq {\frac{2\pi}{3}\quad {or}\quad \frac{4\pi}{3}} < {\omega \quad t} \leq \frac{5\pi}{3}}$

Consequently, the peak common-mode voltage produced by this zero vectorhas been reduced by half, by restricting its usage during the AC cycle.To realize this reduction factor over the entire AC cycle, similarrestrictions are placed on the other zero vectors. This is summarized inthe following table and illustrated in FIG. 14.

Zero Vector Allowable Periods of Application (At, Ab) π/3 < ωt < 2π/3and 4π/3 < ωt < 5π/3 (Bt, Bb) 0 < ωt < π/3 and π < ωt < 4π/3 (Ct, Cb)2π/3 < ωt < π and 5π/3 < ωt < 0

Determination of the switch sets for the zero vector, denoted SW0,applies to both the top and bottom groups of switches in the DC matrixconverter. Determination of which sector the voltage vector lies in isaccomplished with inequality testing. The inequalities that define thesector boundaries are shown in FIG. 14. The sectors, in which SW0=A, aredefined by the following inequality (positive result of test 139 of FIG.15):$\left\lbrack {{Vd} > {{{- {Vq}}\sqrt{3}}\bigcap{Vd}} > {{Vq}\sqrt{3}}} \right\rbrack\bigcup{\left\lbrack {{Vd} < {{{- {Vq}}\sqrt{3}}\bigcap{Vd}} < {{Vq}\sqrt{3}}} \right\rbrack \left\lbrack {{Vd} > {{{Vq}\sqrt{3}}}} \right\rbrack}\bigcup\left\lbrack {{- {Vd}} > {{{Vq}\sqrt{3}}}} \right\rbrack$${{Vd}} > {{{Vq}\sqrt{3}}}$

Similarly, SW0=B is identified by testing the following inequality(positive result of test 140 of FIG. 15);$\left\lbrack {{Vd} > {0\bigcap{Vd}} < {{Vq}\sqrt{3}}} \right\rbrack\bigcup{\left\lbrack {{Vd} < {0\bigcap{Vd}} > {{Vq}\sqrt{3}}} \right\rbrack \left\lbrack {{Vd}^{2} < {{VdVq}\sqrt{3}}} \right\rbrack}\bigcup\left\lbrack {{Vd}^{2} < {{VdVq}\sqrt{3}}} \right\rbrack$${Vd}^{2} < {{VdVq}\sqrt{3}}$

SW0=C is determined by elimination (negative result of test 140 of FIG.15).

If desired, programming may be simplified by noting the similarity tothe algorithm for setting the duty ratios, provided the followingsubstitution is made:

Vd=Vq

Vq=Vd

The zero vector switch selection described hereinbefore with respect toFIGS. 14 and 15 is disclosed and claimed in commonly owned copendingU.S. patent application Ser. No. 09/310,311, filed contemporaneouslyherewith.

Within each modulation period, the order in which the various pairs andsets of switches are operated for the α vector, the β vector, and thezero vector, is immaterial. Thus the order may be α, β, zero; β, α,zero; β, zero, α; or any other order. With the constraint that a switchconducting between one of the AC mains and one of the output terminalsis never shut off until another switch is turned on to conduct from anAC main to that terminal, the relationship of switch pairs (αand β) andsets (zero vectors) illustrated in FIG. 4 (along with FIGS. 9-12 and 14)show that switch commutation is minimized by practicing the presentinvention. For instance, switch At will be turned on as part of the αvector when the α vector is i6 (comprising the leading boundary of phasesector s=0), and remain on during the β portion of each modulationperiod as part of the pair for current vector i1. On the other hand,switch At may be first turned on as part of current vector i1 and remainon as part of current vector i6, within each of the modulation periodswithin the phase sector, s=0. And even if the zero vectors switch set isoperated between the pair of α switches and the pair of β switches, inone modulation period, the At switch, for instance, may be turned on fori6 at the end of one modulation period, and remain on for i1 in thebeginning of the next following modulation period. Thus, in any case,two switches will be turned on only once per modulation period, incontrast with three switches being turned on per modulation period inany schemes heretofore known to the prior art. Thus, the number ofcommutations for switches in forming the non-zero vectors is reduced byone-third. The same relationships exist for the zero vectorcommutations.

Thus, the advantages of reduced commutations offered by the space-vectorapproach of the invention represented in the space-vector diagram shownin FIG. 4 may be combined with the reduced requirements of common-modemagnetic components offered by reduced common-mode voltage realized bycurtailing the allowable periods of application for the zero vectors,shown in said copending U.S. patent application Ser. No. 09/310,311. Thecombined strategy of all allowable vectors, for m*>0, is given in thefollowing table.

Sec- Vector Vector Voltage Zero tor Iα Iβ Angle Relationship Vector 0 i6i1 330-360 VA > VC > VB (C1, C2) (A1, B2) (A1, C2)  0-30 VA > VB > VC(B1, B2) 1 i1 i2 30-60 (A1, C2) (B1, C2) 60-90 VB > VA > VC (A1, A2) 2i2 i3  90-120 (B1, C2) (B1, A2) 120-150 VB > VC > VA (C1, C2) 3 i3 i4150-180 (B1, A2) (C1, A2) 180-210 VC > VB > VA (B1, B2) 4 i4 i5 210-240(C1, A2) (C1, B2) 240-270 VC > VA > VB (A1, A2) 5 i5 i6 270-300 (C1, B2)(A1, B2) 300-330 VA > VC > VB (C1, C2)

Referring to FIG. 4, at small phase angles φ within sector 0, withineach pulse width modulation period, switch At is on for a relativelylong time (along with a switch Bb) in relation to the α vector I6, andit is on for a relatively short time (along with a switch Cb) inrelation to the β vector, I1. At large phase angles φ within sectorzero, the opposite occurs. The switch At remains continuously on for theportions related both to the α vector and the β vector. In the center ofsector 0, the time that the At switch remains on is maximal, giving riseto the duty cycle waveform of FIG. 16(a). FIG. 16(b) shows an exemplaryset of on times for switches at, bt and ct, and FIG. 16(c) illustratesthe instantaneous (unfiltered, idealized) DC output voltage that wouldresult.

The order in which the calculations are performed (FIGS. 8, 13 and 15)is irrelevant to the present invention. Of course, the switch selection(each pair or set) as well as the duration for each pair or set has tobe known before that pair or set can be operated in each modulationperiod. The use of the selection and duration information within thetiming circuit 78 is conventional, being essentially the same as isutilized in AC—AC matrix converters.

The invention has been described in an embodiment in which there are 12switches at+ at−, . . . cb+, cb−, in order to accommodate loads in bothdirections and regeneration. However, the invention may as well beutilized in DC matrix converters driving loads in a single directionwithout regeneration, such as for driving power tools, or in otherapplications.

The present invention has been shown as it may be implemented utilizingn-type, punch-through, insulated gate bipolar transistor power switches.However, the invention may be implemented using p-type transistors, orwith non-punch-through, insulated gate bipolar transistors connected inanti-parallel pairs.

The foregoing patent application and article are incorporated herein byreference.

I claim:
 1. A method of controlling the flow of current through a DCmatrix converter between a DC load and a set of three-phase AC mains,said DC matrix converter comprising a plurality of top switches, eachconnected between a corresponding one of said AC mains and a first DCoutput of said DC matrix converter, and a plurality of bottom switches,each connected between a corresponding one of said AC mains and a secondDC output of said DC matrix converter, comprising: operating saidswitches in a manner so that each switch, when operated to connect acorresponding one of said AC mains to a related specific one of said DCoutputs, remains operated until another switch has operated to connectone of said AC mains to said specific DC output, and so that one of saidtop switches is operated contemporaneously with one of said bottomswitches, said switches being operated in pairs, each pair including atop switch related to one AC main and a bottom switch related to an ACmain other than said one AC main, and said switches also being operatedin sets, each set including a top switch and a bottom switch bothrelated to the same AC main; providing a voltage command signal, V*,indicative of the voltage to be provided by said DC output terminals tosaid load; providing a modulation command, m*, as the ratio of saidvoltage command signal, V*, to the instantaneous magnitude of voltage,V, of said AC mains in stationary d, q coordinates; and providing anin-phase modulation command component, mq=m* cos θ and a quadraturemodulation command component md=m* sin θ; providing a quantitym1=3md/2−mq/2; providing a quantity m2=3md/2+mq/2; providing an in-phasecomponent, Vq, and a quadrature component, Vd, of the instantaneous ACmains voltage in orthogonal coordinates aligned with the phase of agiven one of said AC mains; and providing, when |Vd3|<|Vq|, a firstfraction dα=−m1 if Vq>0 and dα=m1 if Vq<0, and a second fraction dβ=m2if Vq>0 and dβ=−m2 if Vq<0; providing when VdVq3>Vq², said firstfraction dα=−m2 mq if Vq>0 and dα=m2 −mq if Vq<0, and said secondfraction dβ=mq m1if Vq>0 and dβ=−mq −m1if Vq<0; and providing, whenneither |Vd3|<|Vq| nor Vd3>Vq, said first fraction dα=mq −m2if Vq>0 anddα=−mq m2if Vq<0, and said second fraction dβ=−m1 mqif Vq>0 and dβ=−m1−mq if Vq<0; and in each of a continuous sequence of modulation periodswhich are small compared with the period of voltage of said AC mains,operating a first pair of said switches for said first fraction, dα, ofsaid period, operating a second pair of said switches for said secondfraction, dβ, of said period, and operating a set of switches for theremainder of said period.
 2. A method according to claim 1 wherein saidfirst fraction of time precedes said second fraction of time within saidmodulation periods.
 3. A method according to claim 1 wherein theremainder of said period follows said first and second fractions of timewithin said modulation periods.
 4. A method of controlling the flow ofcurrent through a DC matrix converter between a DC load and a set ofthree-phase AC mains, said DC matrix converter comprising a plurality oftop switches, each connected between a corresponding one of said ACmains and a first DC output of said DC matrix converter, and a pluralityof bottom switches, each connected between a corresponding one of saidAC mains and a second DC output of said DC matrix converter, comprising:operating said switches in a manner so that each switch, when operatedto connect a corresponding one of said AC mains to a related specificone of said DC outputs, remains operated until another switch hasoperated to connect one of said AC mains to said specific DC output, andso that one of said top switches is operated contemporaneously with oneof said bottom switches, said switches being operated in pairs, eachpair including a top switch related to one AC main and a bottom switchrelated to an AC main other than said one AC main, and said switchesalso being operated in sets, each set including a top switch and abottom switch both related to the same AC main; in each of a continuoussequence of modulation periods which are small compared with the periodof voltage of said AC mains, operating a first pair of said switches fora first fraction, dα, of said period, operating a second pair of saidswitches for a second fraction, dβ, of said period, and operating a setof switches for the remainder of said period; characterized by theimprovement comprising: providing an in-phase component, Vq, and aquadrature component, Vd, of the instantaneous AC mains voltage inorthogonal coordinates aligned with the phase of a given one of said ACmains; if Vd3< ≧|Vq|, said first pair of switches include a top switchconnected to a third AC main, next advanced in phase from said given oneof said AC mains, but if not, then if Vq>0, said first pair of switchesinclude a top switch connected to said given one of said AC mains, butif neither, then said first pair of switches include a top switchconnected to a second AC main, next delayed in phase from said given oneof said AC mains; if −Vd3>|Vq|, said first pair of switches include abottom switch connected to said third AC main, but if not, then if −Vq<0, said first pair of switches include a bottom switch connected tosaid given one of said AC mains, but if neither, then said first pair ofswitches include a bottom switch connected to said second AC main; if−Vd3>|Vq|, said second pair of switches include a top switch connectedto said second main, but if not, then if Vq>0, said second pair ofswitches include a top switch connected to said given one of said ACmains, but if neither, then said second pair of switches include a topswitch connected to said third AC main; and if Vd3< ≧|Vq|, said secondpair of switches include a bottom switch connected to said second main,but if not, then if Vq<0, said second pair of switches include a bottomswitch connected to said given one of said AC mains, but if neither,then said second pair of switches include a bottom switch connected tosaid third AC main.
 5. A method according to claim 4 wherein said firstfraction of time precedes said second fraction of time within saidmodulation periods.
 6. A method according to claim 4 wherein theremainder of said period follows said first and second fractions of timewithin said modulation periods.
 7. A method of controlling the flow ofcurrent through a DC matrix converter between a DC load and a set ofthree-phase AC mains, said DC matrix converter comprising a plurality oftop switches, each connected between a corresponding one of said ACmains and a first DC output of said DC matrix converter, and a pluralityof bottom switches, each connected between a corresponding one of saidAC mains and a second DC output of said DC matrix converter, comprising:operating said switches in a manner so that each switch, when operatedto connect a corresponding one of said AC mains to a related specificone of said DC outputs, remains operated until another switch hasoperated to connect one of said AC mains to said specific DC output, andso that one of said top switches is operated contemporaneously with oneof said bottom switches, said switches being operated in pairs, eachpair including a top switch related to one AC mains and a bottom switchrelated to an AC main other than said one AC main, and said switchesalso being operated in sets, each set including a top switch and abottom switch both related to the same AC main; providing a voltagecommand signal, V*, indicative of the voltage to be provided by said DCoutput terminals to said load; providing a modulation command, m*, asthe ratio of said voltage command signal, V*, to the instantaneousmagnitude of voltage, V, of said AC mains in stationary d, qcoordinates; and providing an in-phase modulation command component,mq=m* cos θ and a quadrature modulation command component md=m* sin θ;providing a quantity m1=3md/2−mq/2; providing a quantity m2=3md/2+mq/2;providing an in-phase component, Vq, and a quadrature component, Vd, ofthe instantaneous AC mains voltage in orthogonal coordinates alignedwith the phase of a given one of said AC mains; and providing, when|Vd3|>|Vq|, said first fraction dα=−m1 if Vq>0 and dα=m1 if Vq<0, andsaid second fraction dβ=m2 if Vq>0 and dβ=−m2 if Vq<0; providing whenVd3=Vq, said first fraction dα=−m2 mq if Vq>0 and dα=m2 −mq if Vq<0, andsaid second fraction dβ=mq m1if Vq>0 and dβ=−mq −m1if Vq<0; andproviding, when neither |Vd3|<|Vq| nor Vd3>Vq, said first fraction dα=mq−m2if Vq>0 and dα=−mq m2if Vq<0, and said second fraction dβ=m1 mq ifVq> and dβ−m1 −mq if Vq<0; in each of a continuous sequence ofmodulation periods which are small compared with the period of voltageof said AC mains, operating a first pair of said switches for a firstfraction, dα, of said period, operating a second pair of said switchesfor a second fraction, dβ, of said period, and operating a set ofswitches for the remainder of said period; and further comprising: ifVd3< ≧|Vq|, said first pair of switches include a top switch connectedto a third AC main, next advanced in phase from said given one of saidAC mains, but if not, then if Vq>0, said first pair of switches includea top switch connected to said given one of said AC mains, but ifneither, then said first pair of switches include a top switch connectedto a second AC main, next delayed in phase from said given one of saidAC mains; if −Vd3>|Vq|, said first pair of switches include a bottomswitch connected to said third AC main, but if not, then if −Vq<0, saidfirst pair of switches include a bottom switch connected to said givenone of said AC mains, but if neither, then said first pair of switchesinclude a bottom switch connected to said second AC main; if −Vd3>|Vq|,said second pair of switches include a top switch connected to saidsecond main, but if not, then if Vq>0, said second pair of switchesinclude a top switch connected to said given one of said AC mains, butif neither, then said second pair of switches include a top switchconnected to said third AC main; and if Vd3< ≧|Vq|, said second pair ofswitches include a bottom switch connected to said second main, but ifnot, then if Vq<0, said second pair of switches include a bottom switchconnected to said given one of said AC mains, but if neither, then saidsecond pair of switches include a bottom switch connected to said thirdAC main.
 8. A method according to claim 7 wherein said first fraction oftime precedes said second fraction of time within said modulationperiods.
 9. A method according to claim 7 wherein the remainder of saidperiod follows said first and second fractions of time within saidmodulation periods.